1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, to a semiconductor device, which has a trench separation band, and a manufacturing method thereof.
2. Description of the Background Art
Insulating separation bands are provided in many places of a semiconductor substrate in a semiconductor device such as a DRAM (dynamic random access memory), an SRAM (static random access memory) and a flash memory. Though LOCOS (local oxidation of silicon) separation has been in conventional use, as the miniaturization of the above described semiconductor devices has progressed, trench separation bands suitable for miniaturization have come to be exclusively used for separation bands.
Next, a process for a general trench separation band is described in reference to the figures. First, a base silicon oxide layer (SiO2 film) 102, whose thickness is, for example, 50 nm, is formed on a silicon substrate 101. Base silicon oxide layer 102 is formed for the purpose of height adjustment of the trench separation band. Then, a polycrystalline silicon layer 103, whose thickness is 100 nm, is deposited on the base silicon oxide layer. In addition, a silicon nitride layer (SiN film) 104, whose thickness is 300 nm, is deposited thereon (FIG. 15). Silicon nitride layer 104 functions as a stopper layer during CMP polishing.
After this, a photoresist pattern 105 is formed which corresponds to regions where the trench separation bands are desired to be provided. Then, silicon nitride layer 104 is patterned by using this photoresist pattern as a mask (FIG. 16). After this, photoresist pattern 105 is removed. Then, polycrystalline silicon layer 103 and silicon oxide layer 102 are etched by using patterned silicon nitride layer 104 as a mask. Furthermore, a trench 106, whose depth is, for example, 0.5 xcexcm, is created in the silicon substrate by using these patterns as a mask (FIG. 17). Polycrystalline silicon layer 103 makes it easy for an inner wall silicon oxide film to be formed. In addition to this, polycrystalline silicon layer 103 protects the silicon substrate at the time when the silicon oxide film filled into the trench separation band is etched.
After this, the damaged layer on the trench surface is removed and, after that, a silicon oxide film (hereinafter referred to as inner wall oxide film) 107 is formed in the inner wall of the trench with a thickness of, for example, 120 nm (FIG. 18). This inner wall oxide film 107 functions as a short circuit prevention insulating film of silicon substrate 101 as described below. In addition, at the same time, it functions as a layer that relieves stress due to the difference in the thermal expansion coefficients of the filled-in silicon oxide film (hereinafter referred to as filled-in oxide film), which is filled into the trench, and silicon substrate 101.
Next, the above described filled-in insulating layer 108 is deposited with a thickness of 1 xcexcm so as to fill in trench 106, on which inner wall oxide film 107 has been formed (FIG. 19). After this, CMP polishing is carried out by utilizing slurry, whose main component is silicon oxide (SiO2). As for CMP polishing, the polishing rates within the wafer surface area are taken into consideration and polishing is carried out until, at least, silicon nitride layer 104 is exposed (FIG. 20).
At the time of this CMP polishing the unevenness of the polishing rates is taken into consideration and over-etching is carried out to the degree of 10% of the thickness of an HDP (High Density Plasma) film. As a result of this over-etching, in some regions 100 nm of silicon nitride layer 104 is polished off. After this, etching is carried out by using an HF liquid so as to make filled-in oxide film 108 lower by 250 nm for the purpose of adjustment of the height of the trench separation (FIG. 21). Next, the silicon nitride layer, the polycrystalline silicon layer and the base silicon oxide layer are removed. As a result of this, as shown in FIG. 22, a trench separation band, whose height from the silicon substrate surface is approximately 50 nm, that is, in the range of 0 nm to 100 nm, can be formed.
A trench separation band which has a conventional width can be formed by using the above described method. In the formation of the trench separation band with a conventional width, as shown in FIG. 20, the top surface of the trench oxide film and the top surface of the silicon nitride layer become a shared surface.
When a trench silicon oxide layer (hereinafter referred to as trench oxide layer or trench oxide film) is filled into a wide trench in order to form a wide trench separation band by means of the above described method, however, trench oxide layer 108 in a form as shown in FIG. 23 is formed. After this, the trench oxide layer is polished through CMP polishing and silicon nitride layer 104 is exposed. At this time, the top surface of trench silicon oxide film (hereinafter referred to as trench oxide film or trench oxide layer) 108 of the wide trench becomes lower than the top surface of silicon nitride layer 104 so as to form a recess in a dish form (FIG. 24). This trench oxide film is, in some cases, referred to as a filled-in oxide film in the description hereinafter. Concretely, the top surface of filled-in oxide film 108 of the wide trench is, for example, 100 nm lower than the top surface of silicon nitride layer 104.
After this, etching is carried out by using an HF liquid so as to reduce the thickness of the filled-in oxide film by, for example, 250 nm for the purpose of adjustment of the height of the trench separation band. In some cases as a result of this etching by using the HF liquid, as shown in FIG. 25, silicon substrate 101 is exposed beneath an edge portion of base silicon oxide layer 102 in the upper portion of a sidewall of the wide trench. After this, when polycrystalline silicon layer 103 is removed through etching, the exposed portion of the silicon substrate, which is also made of silicon, is etched. As a result of this, the exposed portion of silicon is scooped out in an inward direction and, as shown in FIG. 26, a cavity 111 is created.
In the case that such a scooping out occurs, the wide trench separation band cannot sufficiently function so as to isolate, without fail, respective regions in the silicon substrate by means of an insulating layer. Therefore, a short circuit, or the like, occurs.
A phenomenon wherein a silicon substrate is scooped out due to etching of a filled-in oxide film in a trench separation band, as described above, is known conventionally and several methods for preventing the silicon substrate from being scooped out have been proposed. For example, a method has been proposed wherein the filled-in oxide film is etched after being flattened through polishing so that the difference in the levels of the oxide film in the active region on which semiconductor elements are to be formed (Japanese Patent Laying-Open No. 2000-68365). In this method, however, the creation of a recess in a dish form is not supposed to occur through CMP polishing of the filled-in insulating layer of the wide trench separation band. Therefore, it cannot be used for the formation of the wide trench separation band which is the subject of the present invention.
In addition, a method has been proposed wherein a thermal oxide film, which has strong withstanding properties against etching, is formed not only on the inner walls of the trench but, also, on the side surfaces of the filled-in oxide film which protrudes above the silicon substrate surface (Japanese Patent Laying-Open No. 10-340950). However, this method is not effective in the case that a recess in a dish form occurs through CMP polishing in the filled-in insulating layer of the wide trench separation band.
In addition, in the case that intervals of active regions 130 wherein semiconductor elements are formed become wide, a structure as shown in FIG. 27 is conventionally provided since wide separation regions cannot be manufactured. In FIG. 27 a number of dummy active regions 125 are aligned between active regions 130 so that trench separation band 110 is formed among the regions. The base part is strengthened because of the alignment of dummy active regions 125 so that a recess in a dish form does not occur after the CMP polishing process. Length L1 of one side of the above described dummy active regions is, for example, 2 xcexcm to 5 xcexcm, intervals S1 between dummy active regions are, for example, 2 xcexcm to 5 xcexcm and intervals S2 between dummy active regions and active regions 130 wherein semiconductor elements are formed are, for example, 2 xcexcm to 10 xcexcm.
In the case that the above described dummy active regions are formed it is necessary to prepare a fine, complex pattern on a CAD. In many cases this task on CAD is complex and time consuming.
Furthermore, in the case that wires are arranged on the separation bands, as shown in FIG. 28, one wire is divided into two wires 131, 132 and dummy active regions are aligned in the separation bands in order to avoid the formation of a large separation band. Size L1 of the dummy active regions in FIG. 28 is, for example, 2 xcexcm to 5 xcexcm, intervals S1 between the dummy active regions are, for example, 2 xcexcm to 5 xcexcm, and distances S3 between the dummy active regions and the wires are, for example, 2 xcexcm to 10 xcexcm.
In the case that a structure as described above is adopted, (a) the layout of wires 131, 132 become greatly limited and (b) useless regions, that is to say regions of the width (L1+2S3), are formed between the wires. Such useless regions have become a great hindrance to the miniaturization of semiconductor elements.
The main purpose of the present invention is to provide a manufacturing method of a semiconductor device wherein a trench separation band, wherein no scooping out of the silicon substrate occurs, is formed even when the trench separation band is a wide trench separation band and to provide a semiconductor device which includes such a trench separation band. By achieving this main purpose it becomes unnecessary to arrange complex dummy active regions and a secondary purpose of the invention is to divide wires so as to make it unnecessary to form useless regions.
A manufacturing method of a semiconductor device of the present invention is provided with the steps of forming a multilayer film which includes a silicon oxide layer on the main surface of a silicon substrate, a polycrystalline silicon layer positioned in a layer above the silicon oxide layer and a silicon nitride layer positioned in a layer above the polycrystalline silicon layer. This process is further provided with the step of patterning the multilayer film and, in addition, etching the silicon substrate to create a trench for element separation, the step of oxidizing the surfaces of the inner walls of the trench which includes the sidewalls of the multilayer film so as to form an inner wall silicon oxide film which covers the inner walls and the step of forming a trench oxide layer which fills in the trench covered by the inner wall silicon oxide film and which contacts the top surface of the silicon nitride layer. In addition, this process is provided with the step of polishing the trench oxide layer and the silicon nitride layer through CMP polishing so as to expose the silicon nitride layer to the predetermined thickness of the thickness of the silicon nitride layer and the step of etching the trench oxide film, which is formed by polishing the trench oxide layer through CMP polishing, by a thickness no more than the thickness of the inner wall silicon oxide film for the purpose of adjustment of the height of the trench separation band.
In the above described structure, the silicon substrate is not exposed through etching for the purpose of height adjustment, however the deep central portion of the top surface of the trench oxide film (filled-in oxide film) becomes through the creation of a recess in a dish form by means of a CMP polishing process in the wide trench separation band. In the wide trench separation band the edge portions of the silicon substrate are protected by the inner wall oxide film, which is not changed after formation, and by the trench oxide film, wherein a recess is created in a dish form and which sits on the inner wall oxide film before the etching for height adjustment. That is to say, the edge portions of the silicon substrate are protected by, at least, the inner wall silicon oxide film, which is not changed after formation. In the case that the trench oxide film is etched by a thickness no more than the thickness of the inner wall silicon oxide film through etching for height adjustment, the inner wall silicon oxide film, which is also made of silicon oxide, is not etched completely. Therefore, the edge portions of the silicon substrate are not exposed through the etching for height adjustment of the trench separation band.
After this, a selective etching is carried out for removing the polycrystalline silicon layer on the silicon substrate. In the case that the edge portions of the silicon substrate are exposed, the silicon substrate is etched and is scooped out by the etching liquid for etching the polycrystalline silicon. However, the edge portions of the silicon substrate are not exposed and, therefore, the silicon substrate is not scooped out through this etching.
After removing this polycrystalline silicon layer, the silicon oxide layer as the base is removed through etching and at this time though the trench oxide layer, which is also made of silicon oxide, is etched, the silicon substrate is not etched. Therefore, the silicon substrate is not scooped out.
In summary, in the above structure the edge portions of the silicon substrate are neither exposed after the etching for height adjustment of the trench separation band nor before the etching of the polycrystalline silicon and, therefore, the silicon substrate is not scooped out. Here, in the above described multilayer film, a polycrystalline silicon layer is arranged between the silicon nitride layer, which becomes a stopper layer at the time of CMP polishing, and the base silicon oxide layer, and the reasons for this are as follows. At the time of oxidation processing of the inner walls for forming the inner wall silicon oxide film, the inner wall silicon oxide film is formed through the oxidation of the edge portions of the polycrystalline silicon layer. The inner wall silicon oxide film formed in the edge portions of this polycrystalline silicon layer becomes upwardly raised from the main surface of the silicon substrate in the first trench separation band so that an electric field concentration can be avoided. The above described polycrystalline silicon layer is formed in this manner for the purpose of avoiding electric field concentration.
Here, the above described etching for height adjustment of the trench separation band is an etching for the purpose of adjustment of the height of the trench separation band of a conventional width wherein a recess in a dish form does not occur due to a CMP polishing process. At the time of this etching for height adjustment, a trench separation band of a conventional width is, of course, etched by the same thickness as of the trench oxide film of a wide trench separation band. This etching for height adjustment is adjusted according to the time of immersion in the etching liquid in accordance with the concentration, temperature, or the like, of the etching liquid. In addition, in the case of dry etching, the adjustment is carried out by changing predetermined adjustment factors concerning the etching thickness.
In the method of manufacturing a semiconductor device of the present invention, the sum of the thickness of the silicon nitride layer and the thickness of the polycrystalline silicon layer after CMP polishing can be made greater in comparison with the thickness of the inner wall silicon oxide film by a value no less than the difference gained by subtracting the amount of change of the maximum dispersion of the etching for the purpose of adjustment to a desired height from a desired separation height.
In this structure the silicon substrate is prevented from being scooped out in a wide trench separation band while the height, from the silicon substrate surface, of a trench separation band of the conventional width is made to be approximately 50 nm, that is, the height of the conventional separation band or to be in the range of 0 nm to 100 nm. That is to say, in the trench separation band of the conventional width, the top surface of the trench oxide layer after a CMP polishing process is at the same level as the top surface of the silicon nitride layer. That is to say, when the thickness of the silicon nitride layer after CMP polishing is t1, the thickness of the polycrystalline silicon layer is t2 and the thickness of the silicon oxide layer is t3, the top surface of the trench oxide layer after the CMP polishing process is at the height of (t1+t2+t3) from the silicon substrate surface.
After this, an amount of etching no greater than the thickness of the inner wall silicon oxide film is carried out for height adjustment. When the maximum value of thickness reduction through this etching is d, the height, from the silicon substrate surface, of the top surface of the trench oxide film after etching for height adjustment becomes (t1+t2+t3xe2x88x92d)
After this, the trench oxide film is etched when the silicon oxide layer on the silicon substrate is removed through etching. At the time when the silicon oxide layer on the silicon substrate is removed through etching, the trench oxide film is etched by approximately the same thickness as of the silicon oxide layer. As a result, the height, from the silicon substrate surface, of the top surface of the trench oxide layer becomes (t1+t2xe2x88x92d)
It is desirable for this height to be approximately 50 nm, that is, the height of conventional separation band or, at least, to be in the range of 0 nm to 100 nm. Here, at the time of the etching for height adjustment, the thickness d of the inner wall silicon oxide layer is not etched but, rather, the maximum dispersion amount of the etching for height adjustment, that is to say, for example, the thickness is etched off to be reduced by approximately 20 nm.
In the method of manufacturing a semiconductor device of the present invention, it is preferable for the silicon nitride layer to be formed to a thickness which includes the thickness to be reduced in the CMP polishing.
In this structure the CMP polishing is stopped without fail by the silicon nitride layer, which is a stopper layer in the CMP polishing process and the multilayer film on the silicon substrate can be protected in the etching for height adjustment of the trench separation band.
In the method of manufacturing a semiconductor device of the present invention, the trench oxide layer can be formed so that the etching rate for the trench oxide film in the etching for height adjustment is greater than the etching rate of the inner wall silicon oxide film.
In this structure etching is carried out so as to reduce the trench oxide film to a predetermined thickness and, in addition, protection of the silicon substrate can be ensured by means of the inner wall silicon oxide film. Here, it is not desirable to make the etching rate of the trench oxide layer too small.
In the method of manufacturing a semiconductor device of the present invention, an oxide layer can be formed by using an HDP (high density plasma) method at the time of the formation of the trench oxide layer.
A silicon oxide layer (filled-in oxide film) of high density can be formed by means of an HDP method. Thereby, the insulation of the trench separation band can be ensured. As for this trench insulating layer, a TEOS (tetra ethyl ortho silicate) film may be formed or an HTO (high temperature oxidation) film may be formed by means of a CVD method instead of an HDP film.
In the method of manufacturing a semiconductor device of the present invention, fluoric acid can be used for the etching which is carried out for height adjustment of the trench separation band.
In this structure the trench oxide layer can be selectively etched at a high etching rate. In addition, dry etching may be used for the above described etching for height adjustment of the trench separation band. Though, in some cases, the trench oxide layer cannot be selectively etched through dry etching, the edge portions of the silicon substrate are not exposed as long as the trench oxide layer is etched by an amount that is no greater than the thickness of the inner wall silicon oxide film. The portions of the silicon substrate in the periphery portions of the trench are protected by the silicon nitride layer, the polycrystalline silicon layer and the silicon oxide layer. These portions are not removed as long as the inner wall silicon oxide film is not removed through etching.
In the method of manufacturing a semiconductor device of the present invention, the trench is created in a large separation band region of the silicon substrate, which includes at least one active region in the plan view, through the etching of the separation region between the external periphery walls of the active regions formed along the peripheries of respective active regions included in the large separation band region and the inner periphery walls of the large separation band region formed along the periphery of the large separation band region while the inner wall silicon oxide film is formed on the external periphery walls of the active regions and on the inner periphery walls of the large separation band region so that the trench oxide layer can be formed so as to fill in the above trench.
In this structure it becomes unnecessary to align dummy active regions in the large separation band region and the time consuming task of forming a complex pattern on, for example, a CAD system in order to design the semiconductor device becomes unnecessary.
In the method of manufacturing a semiconductor device of the present invention, the trench can be created in the silicon substrate in a band form so as to include wires contacting the top surface of the interlayer insulating film on the silicon substrate in the plan view.
Conventionally, wires cannot be provided on places where the occurrence of parasitic capacitance is expected because the width of the wires is great and the thickness of the interlayer insulating film is small. Accordingly, the wire layout is greatly limited. In the above structure wide trench separation bands can be provided in the silicon substrate directly below the wires and, thereby, the thickness of the insulating layer can be made very great so that the parasitic capacitance can be ignored. As a result of this, it becomes possible to enlarge the freedom of the wire layout so as to contribute to, for example, the miniaturization of the semiconductor device.
In the method of manufacturing a semiconductor device of the present invention, first and second wires are arranged side by side and the trench can be created as a region in a band form which includes the first and the second wires in the plan view.
In the case that two wires are provided as described above, a dummy active region is aligned between them in the plan view. This dummy active region between these wires is a useless region. In the above structure no dummy active region is arranged between the wires and this can contribute to the miniaturization of the semiconductor device. In addition, the wire layout can be freely carried out and this enlargement of the freedom of the layout can also contribute to the miniaturization of the semiconductor device.
A semiconductor device of the present invention is a device which is provided with a first trench separation band portion and a second trench separation band portion which is wider than the first trench separation band portion. This device is a semiconductor device wherein the first and the second trench separation bands portions are manufactured through any of the above described processes for a semiconductor device of the present invention.
In this structure a wide trench separation band is formed without scooping out the silicon substrate and the height of a trench separation band of the conventional width can be made to be the same height according to a prior art. Therefore, the large separation region, wherein dummy active regions are conventionally aligned, can be formed of the wide trench separation band portion of the present invention. As a result of this, it becomes possible to eliminate the CAD task for forming the alignment to the dummy active regions.
The semiconductor device of the present invention is a device which is provided with a first trench separation band portion and a second trench separation band portion which is wider than the first trench separation band portion on a silicon substrate. In this semiconductor device the position of the top surface of the first trench separation band portion is in a position approximately 50 nm, that is, in the range of 0 nm to 100 nm higher than the silicon substrate surface. In addition, the position of the top surface of the second trench separation band portion is in a position lower than the main surface of the silicon substrate, the thickness of the inner wall oxide film which covers the inner walls of the trench of the second trench separation band portion in the periphery portions of the trench is less than the thickness in the bottom portion of the trench and the second trench separation band portion has a width wherein a recess in a dish form occurs at the time of the CMP polishing of the silicon oxide film, which fills in the second trench portion.
In this structure even in the case that the second trench separation band portion is a large separation region with the width wherein a recess in a dish form occurs at the time of CMP polishing, a wide trench separation band can be formed without scooping out the silicon substrate. At this time, the height of the trench separation band of conventional width can be in a conventional height range. As a result of this, the large separation region can be formed without using dummy active regions so that it becomes possible to omit the CAD task for forming the alignment of the dummy active regions.
In the above described semiconductor device of the present invention, the width of the second trench separation band portion can be 6 xcexcm even in the narrowest place.
Though even in the case of such a narrow width, conventionally, at least one dummy active region must be formed, in the above described structure dummy active regions can be eliminated.
In the above described semiconductor device of the present invention, an active region wherein a semiconductor element is provided is included in the region of the second trench separation band portion and the external periphery walls surrounding the active region are covered with an inner wall silicon oxide film so that the width of the second trench separation band portion is formed of the width of that silicon oxide film which fills in the second trench.
It becomes possible to form the above described large separation region, which includes an active region, of a wide trench separation band of the present invention. As a result of this, the steps of the formation of dummy active regions can be omitted. The width of the wide trench separation band, even in the case the wide trench separation band portion includes an active region, is determined by the width of the trench oxide film which fills in the trench.
The above described semiconductor device of the present invention has an interlayer insulating film and wires contacting the top surface of the interlayer insulating film above the silicon substrate and the second trench separation band is arranged so as to include the wires with band sides running along the wires in the plan view.
In this structure, in some cases, a parasitic capacitance is formed of the wires and the impurity regions in the silicon substrate with the insulating film placed between them so as to become a cause of malfunction of the semiconductor device. Therefore, in some cases, the wire layout is greatly limited. In the above structure the wire layout can be freely carried out. As a result of this, the freedom of layout of wires can be enhanced. Furthermore, it becomes possible, for example, to use this increase in freedom of wire layout for the miniaturization of the semiconductor device.
In the above described semiconductor device of the present invention, wires are formed of a plurality of wires which are parallel to each other and the second trench separation band can be arranged so as to include the plurality of wires with band sides running along the plurality of wires in the plan view.
In this structure the freedom of wire layout can be enhanced. Furthermore, dummy active regions, which occur as useless regions in the conventional structure, provided among the plurality of wires in the plan view can be omitted. As a result of this, it becomes possible to contribute to the miniaturization of the semiconductor device.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.